-------------------------------------------------------------------------------
-- Design Name: lab1_top.vhd
-- Author: Aaron Baxter
-- Design Overview: Hierachial design that implements a 3 bit mux
--   and a 3-8 decoder to light the LEDs.
-- Synthesis Results: Warning on sw6 being unused.  
-- Slice Utilization: 6
-- Functionality: Works as specified
-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hw1_top is
    Port ( sw : in  STD_LOGIC_VECTOR (7 downto 0);
           Led : out  STD_LOGIC_VECTOR (7 downto 0));
end hw1_top;

architecture Behavioral of hw1_top is

	COMPONENT led_decoder
	PORT(
		mux_out : IN std_logic_vector(2 downto 0);          
		Led : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	signal mux_out : std_logic_vector(2 downto 0);

begin

	with sw(7) select
		mux_out(2 downto 0) <= 	sw(2 downto 0) when '1',
								sw(5 downto 3) when others;
								

	led1: led_decoder PORT MAP(
			mux_out => mux_out,
			Led => Led
		);

end Behavioral;

-----------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity led_decoder is
    Port ( mux_out : in  STD_LOGIC_VECTOR (2 downto 0);
           Led : out  STD_LOGIC_VECTOR (7 downto 0));
end led_decoder;

architecture Behavioral of led_decoder is
begin

	with mux_out select
		Led	<= 		"00000001" when "000",
					"00000010" when "001",
					"00000100" when "010",
					"00001000" when "011",
					"00010000" when "100",
					"00100000" when "101",
					"01000000" when "110",
					"10000000" when "111",
					"00000000" when others;


end Behavioral;





